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cy24292 four outputs pci-express clock generator cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-46142 rev. *d revised november 28, 2011 four outputs pci-express clock generator features 25 mhz crystal or clock input four differential 100 mhz pci-express clocks supports hcsl compatible output levels one single-ended 25 mhz output spread spectrum capability on all 100 mhz pci-express clock outputs smbus interface with read back capability 32-pin qfn package operating voltage 3.3 v commercial and industrial operating temperature range functional description cy24292 is a clock generator de vice intended for pci-express applications. the device includes: four 100 mhz differential clocks with hcsl compatible outputs for pci-express, and one single-ended 25 mhz output. using a serially programmable smbus interface, the cy24292 incorporates spread spectrum modulation on all four 100 mhz outputs. the device incorporat es a lexmark spread spectrum profile for maximum electromagnetic interference (emi) reduction. the spread feature or individual outputs can also be disabled using the smbus interface. logic block diagram (100 mhz) (100 mhz) (100 mhz) (100 mhz) clock buffer/ crystal oscillator pcie0n 25m sclk sdata pd_reset# vdd = 475 ohms 1% gnd pll clock synthesizer, dividers, buffers and configuration logic r ref xin/exclkin xout (25 mhz) pcie0p pcie3p pcie2p pcie1p pcie3n pcie2n pcie1n (25 mhz) ref i [+] feedback
cy24292 document number: 001-46142 rev. *d page 2 of 19 contents pin configuration ............................................................. 3 pin definitions .................................................................. 3 smbus serial data interface ............................................ 4 data protocol .................................................................... 4 control registers ............................................................. 6 application information ................................................... 8 crystal recommendations .......................................... 8 crystal loading ........................................................... 8 calculating load capacitors ....................................... 8 current source (iref) refer ence resistor .................... 8 output termination ...................................................... 8 pcb layout recommendations .................................. 9 decoupling capacitors ........... .............. .............. ......... 9 pci-express layout guidelines ...................................... 9 hcsl compatible layout guid elines .......................... 9 absolute maximum ratings .......................................... 10 recommended operation conditions .......................... 10 dc electrical characteristics ........................................ 11 ac electrical characteristics ........................................ 12 test and measurement setup ........................................ 13 single-ended signals ................................................ 13 differential signals ............. ....................................... 13 ordering information ...................................................... 14 ordering code definitions ..... .................................... 14 package diagram ............................................................ 15 acronyms ........................................................................ 16 document conventions ................................................. 16 units of measure ....................................................... 16 document history page ................................................. 17 sales, solutions, and legal information ...................... 19 worldwide sales and design s upport ......... .............. 19 products .................................................................... 19 psoc solutions ......................................................... 19 [+] feedback
cy24292 document number: 001-46142 rev. *d page 3 of 19 pin configuration figure 1. pin diagram - 32-pin qfn cy24292 pcie3p pcie3n 32 31 30 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 1 2 3 4 6 5 pcie0p iref 25m xin/exclkin pd_reset# sdata sclk gnd vdd pcie2n pcie2p pcie1p pcie1n pcie0n vdd vdd xout vdd vdd vdd vdd gnd gnd nc gnd gnd gnd cy24292 32 pin qfn gnd vdd vdd pin definitions pin number pin name pin type description 1 pcie1p output differential 100 mhz pci-express true clock output. high impedance when disabled. 2pcie1noutput differential 100 mhz pci-express complementary clock output. high impedance when disabled. 3 gnd power ground 4 iref output current set for all differential clock drivers. connect 475 ? resistor to ground. 5pcie2noutput differential 100 mhz pci-express complementary clock output. high impedance when disabled. 6 pcie2p output differential 100 mhz pci-express true clock output. high impedance when disabled. 7 gnd power ground 8 vdd power 3.3 v power supply 9pcie3noutput differential 100 mhz pci-express complementary clock output. high impedance when disabled. 10 pcie3p output differential 100 mhz pci-express true clock output. high impedance when disabled. 11 vdd power 3.3 v power supply 12 pcie0p output differential 100 mhz pci-express true clock output. high impedance when disabled. 13 pcie0n output differential 100 mhz pci-express complementary clock output. high impedance when disabled. 14 sclk input smbus clock input 15 sdata input smbus data input 16 vdd power 3.3 v power supply 17 gnd power ground [+] feedback
cy24292 document number: 001-46142 rev. *d page 4 of 19 smbus serial data interface a two-signal serial interface is provided to enhance the flexibility and function of the clock synthesizer. through the serial data interface, various device functions such as clock output buffers can be individually enabled or disabled. the registers associated with the serial data interface initialize to their default setting upon power up, and therefore this in terface is optional. clock device register changes are normally made upon system initialization, if required. this is a ram-based technology which does not keep its value when power is off or during a power transition. data protocol the clock driver serial protocol accepts byte write, byte read, block write, and block read opera tions from the controller. for block write and read operation, the bytes must be accessed in sequential order from lowest to hi ghest byte (most significant bit first) with the ability to stop after any complete byte is transferred. for byte write and byte read op erations, the system controller can access individually indexed bytes. the offset of the indexed byte is encoded in the command code, as described in ta b l e 1 . the block write and block read protocol is outlined in ta b l e 2 , while table 3 outlines the corresponding byte write and byte read protocol. the slave receiver address is 11010010 (d2h) for write and 11010011 (d3h) for read. 18 vdd power 3.3 v power supply 19 gnd power ground 20 pd_reset# input global reset pin. powers down plls, disables outputs and sets the smbus tables to their default state when pulled low. has internal weak pull up. 21 vdd power 3.3 v power supply 22 xin/exclkin input crystal or clock input. connect to 25 mhz fundamental mode crystal or clock. 23 xout output crystal output. connect to 25 mhz f undamental mode crystal. float for clock input. 24 vdd power 3.3 v power supply 25 nc ? no connect. pin has no internal connection. 26 25m output 25 mhz single-ended lvcmos output. pull-down when disabled by pd_reset#. driven low when individually disabled (via smbus byte 0, bit 0). 27 gnd power ground 28 vdd power 3.3 v power supply 29 gnd power ground 30 vdd power 3.3 v power supply 31 gnd power ground 32 vdd power 3.3 v power supply pin definitions (continued) pin number pin name pin type description table 1. command code definition bit description 7 0 = block read or block write operation, 1 = byte read or byte write operation (6:0) byte offset for byte read or byte write operation. for block read or block wr ite operations, these bits must be '0000000' [+] feedback
cy24292 document number: 001-46142 rev. *d page 5 of 19 table 2. block read and block write protocol block write protocol block read protocol bit description bit description 1 start 1 start 2:8 slave address ? 7 bits 2:8 slave address ? 7 bits 9write 9write 10 acknowledge from slave 10 acknowledge from slave 11:18 command code ? 8-bit ?00000000? stands for block operation 11:18 command code ? 8-bit ?00000000? stands for block operation 19 acknowledge from slave 19 acknowledge from slave 20:27 byte count ? 8 bits 20 repeat start 28 acknowledge from slave 21:27 slave address ? 7 bits 29:36 data byte 0 ? 8 bits 28 read 37 acknowledge from slave 29 acknowledge from slave 38:45 data byte 1 ? 8 bits 30:37 byte count from slave ? 8 bits 46 acknowledge from slave 38 acknowledge data byte n/slave acknowledge 39:46 data byte from slave ? 8 bits data byte n ? 8 bits 47 acknowledge acknowledge from slave 48:55 data byte from slave ? 8 bits stop 56 acknowledge data bytes from slave/acknowledge data byte n from slave ? 8 bits not acknowledge stop table 3. byte read and byte write protocol byte write protocol byte read protocol bit description bit description 1 start 1 start 2:8 slave address ? 7 bits 2:8 slave address ? 7 bits 9 write = 0 9 write = 0 10 acknowledge from slave 10 acknowledge from slave 11:18 command code ? 8 bits ?1xxxxxxx? stands for byte operation, bits[6:0] of bits[6:0] the command code represents the offset of the byte to be accessed 11:18 command code ? 8 bits ?1xxxxxxx? stands for byte operation, of the command code represents the offset of the byte to be accessed 19 acknowledge from slave 19 acknowledge from slave 20:27 data byte from master ? 8 bits 20 repeat start 28 acknowledge from slave 21:27 slave address ? 7 bits 29 stop 28 read = 1 29 acknowledge from slave 30:37 data byte from slave ? 8 bits 38 not acknowledge 39 stop [+] feedback
cy24292 document number: 001-46142 rev. *d page 6 of 19 control registers table 4. byte 0: spread spectrum control register bit type at power up outputs affected description notes 7 r/w 1 all 100 mhz pci-express outputs spread select for 100 mhz pci-express clocks 0 = spread off 1 = ?0.5% down 6 r undefined not applicable not used 5 r/w 1 all outputs global oe bit. enables or disables all outputs. 0 = disabled 1 = enabled 4 r undefined not applicable not used 3 r undefined not applicable not used 2 r undefined not applicable not used 1 r undefined not applicable not used 0 r/w 1 single-ended 25 mhz output, 25m oe for single-ended 25 mhz output, 25m. output driven low when disabled. 0 = disabled 1 = enabled table 5. byte 1: control register bit type at power up outputs affected description notes 0 to 7 r undefined not applicable not used table 6. byte 2: control register bit type at power up outputs affected description notes 0 to 7 r undefined not applicable not used table 7. byte 3: control register bit type at power up outputs affected description notes 6,7 r 0 not applicable not used 5 r/w 1 100 mhz pci-express output pcie3 oe for 100 mhz pci-express output pcie3 0 = disabled 1 = enabled 4 r/w 1 100 mhz pci-express output pcie2 oe for 100 mhz pci-express output pcie2 0 = disabled 1 = enabled 3 r 0 not applicable not used 2 r/w 1 100 mhz pci-express output pcie1 oe for 100 mhz pci-express output pcie1 0 = disabled 1 = enabled 1 r/w 1 100 mhz pci-express output pcie0 oe for 100 mhz pci-express output pcie0 0 = disabled 1 = enabled 0 r undefined not applicable not used table 8. byte 4: control register bit type at power up outputs affected description notes 0 to 7 r undefined not applicable not used [+] feedback
cy24292 document number: 001-46142 rev. *d page 7 of 19 the state of the clock outputs u pon assertion of the pd_reset# sig nal from input pin or global oe control bit from byte 0, bit 5 of the smbus is shown in the following table. table 9. byte 5: control register bit type at power up outputs affected description notes 7 r 0 not applicable revision id bit 3 6 r 0 not applicable revision id bit 2 5 r 0 not applicable revision id bit 1 4 r 1 not applicable revision id bit 0 3 r 1 not applicable vendor id bit 3 2 r 0 not applicable vendor id bit 2 1 r 0 not applicable vendor id bit 1 0 r 0 not applicable vendor id bit 0 table 10. byte 6: control register bit type at power up outputs affected description notes 0 to 7 r undefined not applicable not used table 11. power down reset table h/w pd_reset# (pin 24) s/w pd_reset# (byte 0 bit 5) all clock outputs 0 0 disabled, hi-z. 25m has weak pull-down. 0 1 disabled, hi-z. 25m has weak pull-down. 1 0 disabled, hi-z. 25m has weak pull-down. 11 enabled [+] feedback
cy24292 document number: 001-46142 rev. *d page 8 of 19 application information crystal recommendations the cy24292 requires a parallel resonance crystal. substituting a series resonance crystal causes the cy24292 to operate at the wrong frequency and violate the ppm specificat ion. for most applications there is a 300 ppm frequency shift between the series and parallel crystals due to incorrect loading. crystal loading crystal loading plays a critical role in achieving low ppm performance. to realize low ppm performance, consider the total capacitance the crystal sees to calculate the appropriate capacitive loading (cl). figure 2 shows a typical crystal configuration using two trim capacitors. it is important to note that the trim capacitors in series with the crystal are not parallel. it is a common misconception that load capacitors are in parallel with the crystal and are approximately equal to the load capacitance of the crystal. this is not true. calculating load capacitors in addition to the standard external trim capacitors, the trace capacitance and pin capacitance must also be considered to correctly calculate crystal loading. as mentioned in the previous section, the capacitance on each side of the crystal is in series with the crystal. this means the total capacitance on each side of the crystal must be twice the specified crystal load capacitance (cl). while the capacitance on each side of the crystal is in series with the crystal, the trim capacitors (ce1, ce2) must be calculated to provide equal capacitive loading on both sides. figure 2. crystal loading example use the following formulas to calculate the trim capacitor values for ce1 and ce2. cl ................................................... crystal load capacitance cle .............. .............. ............. actual loading seen by crystal using standard value trim capacitors ce ..................................................... external trim capacitors cs ......................................... .....stray capaci tance (terraced) ci ......................................... ................. internal capacitance current source (iref) reference resistor if the board target trace impedance (z) is 50 ? , then for r ref =475 ? (1%) provides iref of 2.32 ma. the output current (i oh ) is equal to 6 iref. output termination the pci-express differential clock outputs of cy24292 are open source drivers and require an external series resistor and a resistor to ground. these resistor values and their allowable locations are explained in detail in the section pci-express layout guidelines on page 9 . table 12. crystal recommendations frequency cut load cap (max) eff series rest (max) drive (max) tolerance (max) stability (max) aging (max) 25.00 mhz parallel 16 pf 30 ? 1.0 mw 30 ppm 10 ppm 5 ppm/yr xtal ce2 ce1 cs1 cs2 x1 x2 ci 1 ci2 clock chip trace 2.8 pf trim 26 pf pin 3 to 6 pf load capacitance (each side) total capacitance (as seen by the crystal) ce = 2 * cl ? (cs + ci) ce1 + cs1 + ci1 1 + ce2 + cs2 + ci2 1 ( ) 1 = cle [+] feedback
cy24292 document number: 001-46142 rev. *d page 9 of 19 pcb layout recommendations for optimum device performance and lowest phase noise, the following guidelines must be observed. 1. each 0.01 f decoupling capacitor must be mounted on the component side of the board as close to the vdd pin as possible. 2. no vias must be used between the decoupling capacitor and the vdd pin. 3. the pcb trace to the vdd pin and the ground via must be kept as short as possible. the distance of the ferrite bead and bulk decoupling from the device is less critical. 4. an optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers (any ferrite beads and bulk decoupling capacitors can be mounted on the back). other signal traces must be routed away from the cy24292. this includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. decoupling capacitors decoupling capacitors of 0.01 f must be connected between vdd and gnd as close to the device as possible. do not share ground vias between components. route power from power source through the capacitor pad, and then into the cy24292 pin. pci-express layout guidelines hcsl compatible layout guidelines figure 3. pci-express device routing note 1. refer to figure 3 . table 13. common recommendations for differential routing differential routing [1] dimension or value unit l1 length, route as non-coupled 50 ? trace 0.5 max inch l2 length, route as non-coupled 50 ? trace 0.2 max inch l3 length, route as non-coupled 50 ? trace 0.2 max inch r s 33 ? r t 49.9 ? table 14. differential routing for pci-express load or connector differential routing [1] dimension or value unit l4 length, route as coupled microstrip 100 ? differential trace 2 to 32 inch l4 length, route as coupled stripline 100 ? differential trace 1.8 to 30 inch l4 l1 l2 l4 l1 l2 l3 l3 output buffer pci express load or connector rs r t r t r s [+] feedback
cy24292 document number: 001-46142 rev. *d page 10 of 19 absolute maximum ratings parameter description condition min max unit v dd supply voltage ?0.5 4.6 v v in input voltage relative to v ss ?0.5 v dd +0.5 v t s temperature, storage n on operating ?65 150 c t j temperature, junction ? 125 c esd hbm esd protection (human body mo del) jedec eia/jesd22-a114-e 2000 ? v ul-94 flammability rating v-0 at 1/8 in. msl moisture sensitivity level 3 recommended oper ation conditions parameter description min typ max unit v dd supply voltage 3.0 ? 3.6 v t ac commercial ambient temperature 0?70 c t ai industrial ambient temperature ?40 ? 85 c t pu power up time for all v dd to reach minimum specified voltage (power ramps must be monotonic) 0.05 ? 500 ms t pd minimum pulse width of pd_reset# input 100 ? ? ns v smb smbus voltage 3.0 ? 3.6 v r reftol tolerance on the 475 ?? r ref resistor that sets output currents on 100mhz ports ?? 1% [+] feedback
cy24292 document number: 001-46142 rev. *d page 11 of 19 note 2. parameters are guaranteed by design and char acterization. not 100% tested in production. dc electrical characteristics unless otherwise stated, v dd = 3.3v 0.3v, ambient temperature = -40 c to 85 c industrial, 0 c to 70 c commercial, r ref = 475 ? parameter [2] description condition min typ max unit v ol1 low level output voltage of 25m clock i ol = 8 ma ? ? 0.4 v v oh1 high level output voltage of 25m clock i oh = ?8 ma v dd ? 0.4 ? ? v v ol2 low level output voltage of 100m clocks hcsl termination (r s = 33 ? , r t = 49.9 ? ) -0.2 0 0.05 v v oh2 high level output voltage of 100m clocks hcsl termination (r s = 33 ??? r t ??? 49.9 ???? 0.65 0.71 0.95 v v ol3 low level output voltage sdata i ol = 4ma ? ? 0.4 v i oh output high current for differential clocks i oh = 6*i ref -13 -15.2 -17 ma v il1 low level input voltage of sclk, sdata -0.3 ? 0.8 v v ih1 high level input voltage of sclk, sdata 2.1 ? v dd +0.3 v v il2 low level input voltage of xin/exclkin, pd_reset# pins -0.3 ? 0.8 v v ih2 high level input voltage of xin/exclkin, pd_reset# pins 2.0 ? v dd +0.3 v i dd operating supply current no load, pd_reset# pin = 1 ? 50 70 ma full load, pd_reset# pin = 1 ? 135 170 ma i ddpd power down current pd_reset# pin = 0 ? 250 350 ? a c in input capacitance all input pins ? 5 ? pf r pu pull up resistor, pd_reset# ? 90 ? k ? r pd pull down resistor, 25m output pd_reset# = 0 50 ? 150 k ? [+] feedback
cy24292 document number: 001-46142 rev. *d page 12 of 19 ac electrical characteristics unless otherwise stated, v dd = 3.3v 0.3v, ambient temperature = -40 c to 85 c industrial, 0 c to 70 c commercial, r ref = 475 ? table 15. single-ended 25 mhz output parameter [2] description condition min typ max unit f out output clock frequency, 25m ? 25 ? mhz t r output rise time [3] 20% to 80% of v dd ?0.51ns t f output fall time [3] 80% to 20% of v dd ?0.51ns t dc output clock duty cycle [3] measured at v dd /2 45 50 55 % t ccj cycle-to-cycle jitter [3] ??200ps t oepd output enable from power dow n reset pd_reset# going high to 99% of final frequency ??2ms t lock clock stabilization from power up measured from 90% of the applied power supply level ?12ms notes 3. measured with cload = 15 pf lumped load 4. measurement taken from differential waveform (pciep minus pcien). either single ended probes with math or a differential pro be can be used. 5. phase jitter is determined using data captured on an oscillo scope at a sample rate of 20 gs/sec, for a minimum 100,000 contin uous clock periods. this data is then processed using the clockjitter 1.3.0 software from pcisig, using the pci_e_1_1 template. 6. measured from -150 mv to +150 mv on the differential waveform (derived from pciep minus pcien). the signal must be monotonic through the measurement region for rise and fall time. the 300 mv measurement window is centered on the differential zero crossing. 7. measurement taken from a single-ended waveform. 8. measured at crossing point where the instantaneous voltage value of the rising edge of pciep equals the falling edge of pcien . 9. refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. refers to all crossing points for this measurement. 10. defined as the total variation of all crossing voltages of rising pciep and falling pcien. this is the maximum allowed varia nce in v cross for any particular system. 11. ppm refers to parts per million and is a dc absolute period accuracy specification. 1 ppm is 1/1,000,000th of 100.000000 mhz exactly, or 100 hz. for 300 ppm then we have an error budget of 30 khz. the period is to be measured with a frequency counter with measurement window set to 100 ms or greater. the 300 ppm applies to systems that do not employ spread spectrum or that use common clock source. for syst ems employing spread spectrum, there is an additional 2500 ppm nominal shift in maximum period resulting from the 0.5% down spread, re sulting in a maximum average period specification of +2800 ppm. 12. defined as the absolute minimum or maximum instantaneous period. this includes cycle-to-cycle jitter, relative ppm tolerance , and spread spectrum modulation. 13. measured at the rising 0v point of the differential signal. skew is the time difference of the rising 0v point between any t wo differential signal pairs. the measurement is taken over 1000 samples, and the average value is used. table 16. differential 100 mhz, hcsl terminated outputs parameter [2] description test condition min typ max unit f out output frequency ? ? 100 mhz sp profile spread modulation profile ? ? lexmark type sp mod spread modulation frequency 30 32 33 khz t ccj cycle-to-cycle jitter [4] ??90ps t phj peak-to-peak phase jitter [4,5] ??86ps t dc output clock duty cycle [4] 45 50 55 % er r rising edge rate [4,6] see notes 5 and 7 0.6 ? 4.0 v/ns er f falling edge rate [4,6] see notes 5 and 7 0.6 ? 4.0 v/ns v cross absolute crossing point voltage [7,8,9] see notes 8, 9, and 10 0.25 0.35 0.55 v v xdelta variation of v cross over all rising clock edges [7,8,10] see notes 8, 9, and 11 ? ? 140 mv t period avg average clock period accuracy [4,11] see notes 5 and 12 -300 ? 2800 ppm t period abs absolute clock period [4,12] see notes 5 and 13 9.847 ? 10.203 ns t oskew all output skew, all pairs [13] measured at v cross point see note 14 ??100ps t oskew p-p pcie0p/n to pcie3p/n skew and pcie1p/n to pcie2p/n skew [13] measured at v cross point see note 14 ??50ps t oepd output enable from power down reset pd_reset# going high to 99% of final frequency ??2ms t lock clock stabilization from power up measured from 90% of the applied power supply level ?12ms [+] feedback
cy24292 document number: 001-46142 rev. *d page 13 of 19 test and measurement setup single-ended signals differential signals figure 5. test load configuration for differential output signal figure 4. test load configuration for single-ended output signal cload 453 ohm 50 ohm cload pciep pcien 475 ohm 33 ohm 50 ohm cload 33 ohm 50 ohm [+] feedback
cy24292 document number: 001-46142 rev. *d page 14 of 19 ordering information ordering code definitions ordering code package type production flow pb-free cy24292lfxc 32-pin qfn commercial, 0 c to 70 c CY24292LFXCT 32-pin qfn tape and reel commercial, 0 c to 70 c cy24292lfxi 32-pin qfn industrial, ?40 c to 85 c cy24292lfxit 32-pin qfn tape and reel industrial, ?40 c to 85 c t = tape and reel, blank = tube configuration specific identifier (factory programmed) temperature range: x = c or i c = commercial = 0 c to 70 c; i = industrial = ?40 c to 85 c pb-free x = f or blank f = field programmable; blank = factory programmed package: l = 32-pin qfn part identifier company id: cy = cypress 24292 cy x x -xxx l t x [+] feedback
cy24292 document number: 001-46142 rev. *d page 15 of 19 package diagram figure 6. 32-pin qfn (5 5 0.55 mm) lq 32 3.5 3.5 e-pad package outline, 001-42168 001-42168 *d [+] feedback
cy24292 document number: 001-46142 rev. *d page 16 of 19 acronyms document conventions units of measure table 17. acronyms used in this document acronym description eia electronic industries alliance emi electromagnetic interference esd electrostatic discharge hcsl host clock signal level jedec joint electron devices engineering council lvcmos low voltage complementary metal oxide semiconductor oe output enable pci peripheral component interconnect pll phase-locked loop qfn quad-flat no-leads ram random access memory table 18. units of measure symbol unit of measure c degree celsius khz kilohertz k ? kilohm mhz megahertz ? f microfarad ma milliampere ms millisecond mv millivolt ns nanosecond ? ohm % percent pf picofarad ppm parts per million ps picosecond vvolt [+] feedback
cy24292 document number: 001-46142 rev. *d page 17 of 19 document history page document title: cy24292, four outputs pci-express clock generator document number: 001-46142 rev. ecn orig. of change submission date description of change ** 2490167 pyg / dpf / aesa see ecn new data sheet. *a 2507681 dpf / aesa 05/23/2008 updated pin configuration (changed pinout based on pcie_bonding_rev g). updated dc electrical characteristics (added note 2 and referred the same note in parameter column, added hcsl termination in condition column for v ol2 , v oh2 ). updated ac electrical characteristics (updated note 3, added note 8 and referred the same note in t dc parameter in table 16 , changed cload from 2 pf to 4 pf in a note below, added maximum value of v xdelta (140 mv) in the table 16 ). updated data sheet template. *b 2811340 cxq 12/03/2009 removed ?preliminary? from title. updated pin definitions (added explanation of 25 m output disable feature). updated control registers (changed default setting (at power up column) for bit 7 in ta b l e 4 to ?1?, changed description of bit 5 in table 4 to ?global oe bit?, added explanation of 25m out put disable feature in table 4 , changed unused bits (type column) from r/w to r in table 7 , changed default setting (at power up column) for bit 4 in table 9 to ?1?, added explanati on of 25m output disable feature in table 11 ). updated the sub-section crystal recommendations under the main section application information (added ?max? to load cap and eff series rest columns in table 12 ). updated sub-section ?lvds compatible layout guidelines? under the main section pci-express layout guidelines (changed ?lvds down device? to ?lvds device? in all instances). updated absolute maximum ratings (changed maximum value of t j parameter to 125 c). updated recommended operation conditions (added v smb and r reftol parameters and its details). updated dc electrical characteristics (added r ref value to conditions at top, removed v ohsd and v olsd parameters and their details, changed maximum value of v oh2 parameter from 0.85 v to 0.95 v, added v ol3 parameter and its details, changed typical value of i oh parameter from ?14.2 ma to ?15.2 ma, added minimum value of v il1 parameter, changed maximum value of v il1 parameter from 1 v to 0.8 v, changed minimum value of v ih1 parameter from 2.2 v to 2.1 v, added typical and maximum values for i dd no load and full load parameters, changed typical value of i ddpd parameter from tbd to 250 a, changed maximum value of i ddpd parameter from tbd to 350 a, added r pu parameter and its details, changed r pd parameter to apply to 25m output only). updated ac electrical characteristics (added r ref value to conditions at top, removed f err parameter and its details in ta b l e 1 5 , added sp profile parameter and its details in table 16 , added minimum and maximum values for sp mod parameter, changed maximum value of t ccj parameter from 100 ps to 90 ps in table 16 , added t phj parameter and its details in table 16 , changed t r and t f parameters and its details into er r and er f parameters in ta b l e 1 6 , removed t rfmatch parameter and its details in ta b l e 1 6 , splitted t oskew parameter into two parameters namely t oskew all and t oskew p-p parameter and also changed their details in ta b l e 1 6 , added minimum value of v cross parameter and also changed the description of the same parameter in table 16 , changed description of v xdelta parameter in table 16 ). updated package diagram (to spec 001-42168 rev *c). fixed various typos. *c 2901711 kvm 05/14/10 updated package diagram . [+] feedback
cy24292 document number: 001-46142 rev. *d page 18 of 19 *d 3448896 puru 11/28/2011 updated features (removed lvds related information). updated functional description (removed lvds related information). updated output termination under application information (removed lvds related information). removed the sub-section ?lvds compatible layout guidelines? under the main section pci-express layout guidelines . added ordering code definitions . added acronyms and units of measure . updated in new template. document history page (continued) document title: cy24292, four outputs pci-express clock generator document number: 001-46142 rev. ecn orig. of change submission date description of change [+] feedback
document number: 001-46142 rev. *d revised november 28, 2011 page 19 of 19 all products and company names mentioned in this document may be the trademarks of their respective holders. cy24292 ? cypress semiconductor corporation, 2008-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

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